Mechanical stresses within a semiconductor device substrate can be used to modulate device performance. For example, in silicon, hole mobility is enhanced when the film is under compressive stress, while the electron mobility is enhanced when the silicon film is under tensile stress. Therefore, compressive and/or tensile stresses can be advantageously created in the channel regions of a p-FET and/or an n-FET in order to enhance the performance of such devices.
However, the same stress component, either compressive or tensile stress, discriminatively affects the performance of a p-FET and an n-FET. In other words, compressive stress enhances the performance of the p-FET, but adversely impacts the performance of the n-FET, while tensile stress enhances the performance of the n-FET, but adversely impacts the performance of the p-FET. Therefore, p-FET and n-FET require different types of stresses for performance enhancement, which imposes a challenge for concurrent fabrication of high performance p-FET and n-FET devices, due to the difficulty in concurrently applying compressive stress to the p-FET and tensile stress to the n-FET.
One conventional approach for creating desired compressive and tensile stresses in channel regions of p-FET and n-FET devices is to cover the p-FET and the n-FET devices with compressively and tensilely stressed dielectric films, respectively, so that tensile and compressive stresses can be respectively applied to the n-FET and p-FET devices.
However, the tensilely and compressively stressed dielectric films in the conventional CMOS devices are typically patterned by lithography and etching, which are prone to misalignments and may result in significant overlay errors (e.g., in the range of about ±20 nm for the 45 nm node devices). Consequently, the tensilely stressed dielectric layer and the compressively stressed dielectric layer cannot be perfectly aligned with each other at their edges, and the boundary region where the tensilely and compressive stressed dielectric layers meet typically contains either an overlap or a gap between these two layers.
FIG. 1A shows a top view of a conventional CMOS device that comprises a p-FET and an n-FET, and FIG. 1B shows a cross-sectional view of the conventional CMOS device through line A-A. Specifically, such a conventional CMOS device comprises a p-FET active region 102 and an n-FET active region 104 that are separated from each other by an isolation region 111. A common gate structure that comprises a patterned gate conductor 106 and a gate metal silicide layer 107 extend over both active regions 102 and 104 and across the isolation region 111. Gate dielectrics 122 and 142 respectively isolate the p-FET active region 102 and the n-FET active region 104 from the patterned gate conductor 106.
On one hand, a compressively stressed silicon nitride layer 128 selective overlays the p-FET active region 102, but not the n-FET active region 104. On the other hand, a tensilely stressed silicon nitride layer 148 selectively overlays the n-FET active region 104, but not the p-FET active region 102. An optional etch stop layer 149, which preferably comprises a low temperature oxide (LTO), is provided over the tensilely stressed silicon nitride layer 148. As shown in FIG. 1B, the compressively and tensilely stressed silicon nitride layers 128 and 148 are not perfectly aligned at their edges but overlap significantly at the boundary region 103. The misalignment between the compressively and tensilely stressed silicon nitride layers 128 and 148 may also form a gap (not shown) at the boundary region 103.
In the incident that the tensilely and compressively stressed dielectric layers overlap, as shown hereinabove in FIG. 1B, the boundary region has a dielectric layer thickness that is twice of the thickness of the dielectric layer in other regions, which may cause insufficient contact etch. Specifically, if a metal contact is formed over the boundary region, such a metal contact may not be able to extend through the thick dielectric layer located on the boundary region and therefore fails to make contact to the underlying FET components (e.g., the gate conductors or the source/drain of the FETs).
In the alternative incident that a gap is formed between the tensilely and compressively stressed dielectric layers, the etching process used for forming the metal contact opening through the tensilely or compressively stressed dielectric layer may punch through the FET components that are exposed through the gap between the tensilely and compressively stressed dielectric layers. Further, the gap may allow sodium and other contaminants to diffuse into the exposed FET components and thereby causes degradation of the device performance.